FIG. 18 is a diagram illustrating a prior art variable delay circuit. In the figure, reference numerals 1.sub.1 to 1.sub.n designate n delay gates for delaying an input signal for a predetermined time. Reference numeral 100 designates a gate chain comprising the delay gates 1.sub.1 to 1.sub.n connected in series each other. Reference numeral 150 designates an n:1 selector which receives the signals from the connection nodes of respective gates of the gate chain 100 and selects one among the signals to selectively output it. Reference numeral 151 designates a select signal generating circuit for generating a signal for controlling the n:1 selector 150.
A description is given of the operation. A pulse signal input to the input terminal IN of the first stage delay gate 1.sub.1 of the gate chain 100 transmitted through the gate chain 100, which is delayed by the respective delay gates, and the pulse signals at the connection nodes of the respective delay gates are input to the n:1 selector 150. Since a selection data is given to the n:1 selector 150, a pulse signal having a predetermined delay against the pulse signal input to the input terminal IN of the first stage gate 1.sub.1 of the gate chain 100 is output to the output terminal OUT of the n:1 selector 150 in accordance with the control signal from the select signal generating circuit 151.
The prior art variable delay circuit constructed as described above has the following problems. Particularly, the minimum delay time that can be varied, i.e., the resolution of such variable delay circuit, is regulated by the delay time (hereinafter referred to as t.sub.di) of respective delay gates constituting the gate chain 100. Actually, the delay resolution becomes larger than the delay time t.sub.di due to the parasitic capacitance of wiring as shown in FIG. 19. In FIG. 19, reference characters 1.sub.k, 1.sub.k+1 designate k-th and (k+1)-th gates, respectively, included in the gate chain 100. Reference character CL.sub.2k designates a parasitic capacitance due to the wiring for connecting the output of the delay 1.sub.k to the input of the delay 1.sub.k+1, and reference character CL.sub.2k designates a parasitic capacitance due to the wiring for connecting the output of the delay gate 1.sub.k to the n:1 selector 150. Therefore, the delay time in the k-th gate 1.sub.K becomes the sum of the gate delay t.sub.di and the load delay due to the parasitic capacitance CL.sub.1K and CL.sub.2K, resulting in a reduction in the resolution of the variable delay circuit, i.e., an increase in each gate delay time. Since the increment of delay time due to the parasitic capacitance amounts to 0.5.about.1.5 times the gate delay t.sub.di, the resolution of such variable delay circuit becomes 1.5.about.2.5 times the gate delay time t.sub.di, which is so large as to be non-negligible.
As a countermeasure to this reduction in resolution, it is suspected to suppress the reduction in resolution due to reduction of the delay time t.sub.di of the delay gate. However, in order to reduce the delay time t.sub.di of the delay gate, it is required to increase the size of the transistors constituting the delay gate, resulting in an increase in power dissipation.